matmul-analysis/cases_demo.csv at main

Files

admin b0b48b9073 Fix #36 : MergeBatch 合并搬移效率收益建模 (move_eff) + t_cmd_ns 置 0

用户澄清: MergeBatch vs IterBatch 的本质区别不只是 DMA 命令数 —— 合并 b0 个
batch 的左/右矩阵一起搬入 L1, 使单块 tile = nValue*dValue*dt 放大 b0 倍 (堆叠
方向视转置: A ND 非转置沿 M(nValue), B ND 非转置沿 N(dValue)), 搬移效率更高,
即便 T_cmd=0 也有效益。

- models.move_eff: 单命令搬移效率 eff = min(1, tile/min_TileSize) (16KB 饱和,
  与进入条件4效率下限语义同源); gm_move_time 按 A/B 两侧字节加权
  t = (V_A/eff_A + V_B/eff_B)/BW_gm; 只影响时间列, GM 字节量仍 = V_in
- IterBatch: l1_form 补驻留侧返回; move_tiles 分侧口径 (a/b 双侧整K, c 驻留侧
  整K+对侧k_l1, d 双侧k_l1), evaluate 接入效率加权
- MergeBatch: 合并 tile 放大 b0 倍接入效率加权; beats_iterbatch 净收益 =
  命令节省(cmds差×T_cmd) + 效率节省(t_data差) − drain惩罚, K截断且效率打平且
  T_cmd>0 时严格退化为 v1.1 §4.5 闭式; 退役 T_cmd<=0 策略特判
- router: 退役 "T_cmd<=0 策略优先 MergeBatch" 覆盖, 时延模型统一终审
- hardware: t_cmd_ns 50 -> 0 (未标定按 0; 合并收益不再依赖 T_cmd 估计值)
- 作用域: 仅切B 两分支接入 (逐命令 tile 小、效率差显著); ASW/StreamK 单命令
  tile 通常已饱和, 极端小 tile 走 issue#34 效率降级标注通道
- 用户 case 家族 B=128,M=1~16,N=128,K=512: m=1~8 -> MergeBatch (效率节省
  ~0.61us > drain), m=16 -> IterBatch (iter A tile 恰达 16KB 饱和, 效率打平,
  drain 决定); 分界与时延全家族一致
- demo: merge_demo_k_trunc 形状 (2048,32,32,256)->(2048,16,64,128) (原形状
  两侧 tile 均已 16KB 饱和, t_cmd=0 下无收益转 IterBatch; 新形状 iter A tile
  4KB eff=0.25 vs 合并 16KB eff=1.0, 保持 MergeBatch 胜出演示且仍 K截断)
- 测试: 74/74 (新增 TestIssue36 5 例: 效率曲线/字节不变/效率差胜出/家族;
  TestArbitration/TestZeroCmdHandling 按 t_cmd=0+效率语义重写; TestIssue35
  家族期望更新)
- 文档: 01_MergeBatch §4/§5 效率模型+泛化净收益; 02_IterBatch 口径注;
  00_总纲胜出条件; 01_软件架构 T_cmd 标定说明; 05 时间列效率口径注; README 要点
- 验证: examples 重生成可复现 0 diff; 压力 10000 例 0 崩溃/0 NaN/0 违规/
  0 GM<V_in, 七分支覆盖 (MergeBatch 386 例)

2026-09-07 21:09:49 +08:00

2.8 KiB

Raw Permalink Blame History

1	case_id	batch_a	batch_b	m	n	k	dtype_a	dtype_b	dtype_c	out_nd
2	to_matmul_demo	1	1	2048	2048	2048	bf16	bf16	bf16
3	special_k0_demo	128	128	256	256	0	bf16	bf16	bf16
4	special_k1_demo	128	128	256	256	1	bf16	bf16	bf16
5	merge_demo_k_trunc	2048	2048	16	64	128	bf16	bf16	bf16
6	merge_iter_arbitrate	128	128	64	64	512	bf16	bf16	bf16
7	iter_demo_form_b	128	128	64	64	256	bf16	bf16	bf16
8	iter_demo_form_d	64	64	64	64	8192	bf16	bf16	bf16
9	streamk_demo	4	4	128	128	10240	bf16	bf16	bf16
10	asw_demo_full	2	2	8192	8192	1024	bf16	bf16	bf16
11	asw_demo_reduce_core	16	16	256	256	128	bf16	bf16	bf16
12	b4_m1_n128_k256	4	4	1	128	256	bf16	bf16	bf16	1
13	b8_m2_n192_k128	8	8	2	192	128	bf16	bf16	bf16	1
14	b16_m4_n256_k192	16	16	4	256	192	bf16	bf16	bf16	1
15	b32_m8_n128_k256	32	32	8	128	256	bf16	bf16	bf16	1
16	b64_m16_n256_k512	64	64	16	256	512	bf16	bf16	bf16	1
17	b128_m8_n192_k256	128	128	8	192	256	bf16	bf16	bf16	1
18	b32_m16_n8192_k7168	32	32	16	8192	7168	bf16	bf16	bf16	1
19	b4_m1_n8192_k8192	4	4	1	8192	8192	bf16	bf16	bf16	1
20	b16_m2_n4096_k7168	16	16	2	4096	7168	bf16	bf16	bf16	1
21	b32_m64_n64_k7168	32	32	64	64	7168	bf16	bf16	bf16	1
22	b64_m1024_n1024_k7168	64	64	1024	1024	7168	bf16	bf16	bf16	1
23	b128_m2048_n2048_k1536	128	128	2048	2048	1536	bf16	bf16	bf16	1
24	b64_m1024_n8192_k2048	64	64	1024	8192	2048	bf16	bf16	bf16	1
25	b32_m1024_n1024_k512	32	32	1024	1024	512	bf16	bf16	bf16	1
26	b128_m4096_n4096_k8192	128	128	4096	4096	8192	bf16	bf16	bf16	1
27	b32_m8192_n4096_k7168	32	32	8192	4096	7168	bf16	bf16	bf16	1
28	b32_m2048_n2048_k8192	32	32	2048	2048	8192	bf16	bf16	bf16	1
29	b64_m4096_n2048_k128	64	64	4096	2048	128	bf16	bf16	bf16	1
30	b16_m1024_n1024_k8192	16	16	1024	1024	8192	bf16	bf16	bf16	1
31	b4_m32768_n128_k128	4	4	32768	128	128	bf16	bf16	bf16	1
32	b8_m32768_n2048_k512	8	8	32768	2048	512	bf16	bf16	bf16	1
33	b4_m131072_n128_k128	4	4	131072	128	128	bf16	bf16	bf16	1
34	b8_m131072_n1024_k256	8	8	131072	1024	256	bf16	bf16	bf16	1
35	b16_m32768_n8192_k7168	16	16	32768	8192	7168	bf16	bf16	bf16	1
36	b4_m32768_n128_k8192	4	4	32768	128	8192	bf16	bf16	bf16	1
37	b32_m131072_n8192_k128	32	32	131072	8192	128	bf16	bf16	bf16	1
38	b64_m32768_n8192_k1536	64	64	32768	8192	1536	bf16	bf16	bf16	1
39	b8_m131072_n8192_k8192	8	8	131072	8192	8192	bf16	bf16	bf16	1
40	b8_m16_n7168_k1536	8	8	16	7168	1536	bf16	bf16	bf16	1
41	b64_m1024_n7168_k7168	64	64	1024	7168	7168	bf16	bf16	bf16	1
42	b32_m8192_n8192_k7168	32	32	8192	8192	7168	bf16	bf16	bf16	1
43	b8_m4096_n4096_k128	8	8	4096	4096	128	bf16	bf16	bf16	1
44	b128_m8192_n8192_k7168	128	128	8192	8192	7168	bf16	bf16	bf16	1
45	special_k1_b64	64	64	8192	512	1	bf16	bf16	bf16	1

2.8 KiB Raw Permalink Blame History

2.8 KiB

Raw Permalink Blame History